CMOS DAC with high impedance differential current drivers

ABSTRACT

High-performance, digital-to-analog conversion (DAC) suitable for use in systems implemented with low-voltage, low-power integrated circuit fabrication processes is disclosed. Encoder circuitry receives a binary number for which an analog representation is sought. Segments of the binary number are thermometer encoded and complemented to provide signals to drive analog conversion circuitry. The analog conversion circuitry includes sets of current cells, with each cell in a set contributing an equal amount to one or the other of the complementary legs of the analog output of the converter. Each current cell is a fully differential current switch with charge canceling, fed by a regulated cascode current source. The regulated cascode current source offers uncharacteristically high impedance that contributes to good circuit performance even in low-voltage, low-power implementations. Other design factors of the current cell contribute significantly to overall performance. Hierarchical gradient symmetry cancellation techniques are also employed to reduce integral non-linearity attributable to process-related surface gradients.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates to electronic devices and in particular, tothose employing digital-to-analog conversion circuitry.

[0003] 2. Description of Related Art

[0004] Modem electronic systems are typically realized as a complete“system on a chip.” Such systems typically integrate analog and digitalfunctionality onto the die of a single integrated circuit. Such systemsoffer lower cost, power, and size benefits to the customer.

[0005] Often a system will be based on a digital signal processing (DSP)core that implements system functionality through the use of discretemathematical algorithms that are realized through hardware, firmware, orprogrammable means. In order for the system to interface to analog basedcontinuous signals, such systems typically employ the use of adigital-to-analog converter (DAC). Examples of such systems includedirect digital synthesis (DDS) products, TDMA/CDMA wirelesscommunication systems, as well as audio and video devices.

[0006] CMOS continues to be the dominant process used to fabricateintegrated circuits that contain such systems-on-a-chip. Driven by thedesire for further miniaturization, advances in CMOS fabricationprocesses continue to lead to integrated circuits with lower and loweroperating voltage and power specifications. While digital circuitdesigns can readily be transported to a more advanced process, analogcircuit designs often produce poorer results when transported, or cannotbe transported at all.

[0007] Traditional circuit designs for digital-to-analog converterssuffer in this respect and generally perform poorly when moved toadvanced CMOS fabrication processes. Consequently, there is a need inthe art for a digital-to-analog converter providing both good AC and DCperformance characteristics, and occupying minimal die space, whenimplemented using advanced integrated circuit fabrication processes.

SUMMARY OF THE INVENTION

[0008] The invention may be employed to provide high-performancedigital-to-analog conversion suitable for use in systems implementedwith low-voltage, low-power integrated circuit fabrication processes.The digital-to-analog converter embodiment described herein includesencoder circuitry and analog conversion circuitry. The encoder circuitryreceives a binary number for which an analog representation is sought.Segments of the binary number each feed into a binary-to-thermometerencoder. Each binary-to-thermometer encoder turns on the number ofoutput signals that corresponds to the value represented at its inputs.Latch elements latch the output signals of each binary-to-thermometerencoder, and present each signal and its complement as outputs to theanalog conversion circuitry.

[0009] The analog conversion circuitry includes a set of currentswitching cells for each segment of the binary number fed to abinary-to-thermometer encoder. Each cell in a set contributes an equalamount to the analog output of the converter. Each cell is controlled byone of the output signals of the encoder circuitry latches and itscomplement, to contribute its total weight to one or the other of thecomplementary outputs of the converter.

[0010] Each current cell is a fully differential current switch withcharge canceling, fed by a regulated cascode current source. Theregulated cascode current source receives its input current from amaster current bias circuit through a pair of mirror transistors. Theregulated cascode current source offers uncharacteristically highimpedance that contributes to good circuit performance even inlow-voltage, low-power implementations. Other design factors of thecurrent cell contribute significantly to overall performance.

[0011] Hierarchical gradient symmetry cancellation techniques areemployed to assign switching order assignments to the cells within eachset in order to reduce integral non-linearity attributable toprocess-related surface gradients.

[0012] These and other purposes and advantages of the present inventionwill become more apparent to those skilled in the art from the followingdetailed description in conjunction with the appended drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 is a block diagram of a digital-to-analog converter.

[0014]FIG. 2 is a schematic diagram of a master current bias circuit.

[0015]FIG. 3 is a schematic diagram of a current cell circuit.

[0016]FIG. 4 illustrates the layout orientation of current cell matricesand the relative switching order among the cells in each matrix.

[0017] In the figures just described, like parts appearing in multiplefigures are numbered the same in each figure.

DETAILED DESCRIPTION

[0018] The present invention provides improved circuit design forelectronic devices requiring low-voltage digital-to-analog conversion.In the following description, numerous details are set forth in order toenable a thorough understanding of the present invention. Many suchdetails relate to an embodiment of the present invention using a 3.3Volt CMOS fabrication process to implement digital-to-analog conversionfor a 10-bit binary value. However, it will be understood by those ofordinary skill in the art that these specific details are not requiredin order to practice the invention. Further, well-known elements,devices, process steps and the like are not set forth in detail in orderto avoid obscuring the present invention.

[0019]FIG. 1 is a block diagram of a digital-to-analog converter (DAC).Digital-to-analog converter 100 comprises encoder circuitry 110, andanalog conversion circuitry 160. Encoder circuitry 110 further comprisesdata register 120, binary-to-thermometer encoders 130, 132, latches 140,142, inverter 112, and interconnecting signal pathways 122, 124, 134,136, 150, 152, 154, 156. Analog conversion circuitry 160 furthercomprises external bias current connection 161, master current biascircuitry 162, current cell matrices 170, 172, signal pathways 180, 182,184, 186, and current summing nodes 190, 192.

[0020] Encoder Circuitry

[0021] Encoder circuitry 110 functions to receive a binary number at itsinput 101 and to present complementary signal pairs at its outputs150-156 that are representative of the received binary number. Thebinary number is the digital value for which the DAC is to produce ananalog counterpart. The complementary pairs will be used by the analogconversion circuitry to turn on and off individual cells that contributeto the complementary analog output of the DAC.

[0022] Operation of the various circuit elements within encodercircuitry 110 are synchronized by means of a clock signal presented atinput 102. Data register 120 temporarily stores the incoming binarynumber at the rising edge of the clock signal. In the presentlydescribed embodiment, data register 120 is a 10-bit register, permittingthe binary number to have a maximum value of 2¹⁰−1, or 1023 (i.e., 1024possible values including zero).

[0023] Upon storage by the data register 120, the 10 bits representingthe binary number are communicated over signal pathways 122, 124 tobinary-to-thermometer encoders 130,132. Binary-to-thermometer encoders130, 132 are also referred to as unit encoders, herein. Each unitencoder operates such that the number of bits turned on at its output isthe same as the numeric value presented at its input. The numeric valuepresented at its multi-bit input is presumed to be a binary number. Abinary number has a least significant bit with a unit value (i.e.,2⁰=1), and each successive bit represents twice the numeric value of thepreceding bit. When the number is unit coded all bits share the samesignificance, i.e., the unit value.

[0024] A least significant segment of the binary number stored inregister 120, comprising the four least significant bits (LSB), arecommunicated to LSB unit encoder 132 over signal pathway 124. Signalpathway 124 communicates four bits in parallel. LSB unit encoder 132converts the 4-bit input to a 16-bit (2⁴=16), unit coded output. Notethat one of the 16 output bits will always be in the off state and isincluded for design convenience. While the 4-bit input can represent 16possible values, one of those values is zero. Accordingly, the highestnumeric value that can be represented is 15, so at most 15 unit codedoutputs will be in the on state.

[0025] A most significant segment of the binary number stored inregister 120, comprising the six most significant bits (MSB), arecommunicated to MSB unit encoder 130 over signal pathway 122. Signalpathway 122 communicates six bits in parallel. MSB unit encoder 130converts the 6-bit input to a 64-bit (2⁶=64), unit coded output. Notethat one of the 64 output bits will always be in the off state and isincluded for design convenience. While the 6-bit input can represent 64possible values, one of those values is zero. Accordingly, the highestnumeric value that can be represented is 63, so at most 63 unit codedoutputs will be in the on state.

[0026] Each of unit encoders 130, 132 performs and completes theencoding operation during the “on” state of the master clock signal thatfirst triggered the storage of a binary number in register 120.Completion of the encoding operation includes presenting outputs in asettled and static state. In the described embodiment, unit encoders130, 132 were coded in the Verilog programming language and synthesizedinto transistor-based hardware.

[0027] Unit encoder 130 communicates its output to MSB latch circuitry140 over signal pathway 134. Signal pathway 134 communicates 64 bits inparallel. Unit encoder 132 communicates its output to LSB latchcircuitry 142 over signal pathway 136. Signal pathway 136 communicates16 bits in parallel.

[0028] MSB latch circuitry 140 and LSB latch circuitry 142 function as“slave” registers. The clock signal that drives these registers is aninverted version of the master clock signal that drives register 120.The inversion of the master clock signal is implemented through simpleinverter 112. MSB latch circuitry 140 and LSB latch circuitry 142 storetheir input signals communicated over signal pathways 134 and 136,respectively, on the rising edge of the inverted master clock signal.The MSB 140 and LSB 142 latch circuitry present stable output values toanalog conversion circuitry 160 for a first binary number during thetime a second binary number is being stored by register 120 and encodedby unit encoders 130, 132.

[0029] The MSB 140 and LSB 142 latch circuitry further produce acomplementary pair of outputs for each bit of their inputs. The firstoutput signal of the complementary pair is identical in value to thecorresponding input bit. The second output signal of the complementarypair is the complement, or inverse, of the value of the correspondinginput bit. MSB latch circuitry 140 communicates the non-inverted signalsof the complementary pairs on signal pathway 150, and the invertedsignals of the complementary pairs on signal pathway 152, to the MSBcurrent cell matrix 170. LSB latch circuitry 142 communicates thenon-inverted signals of the complementary pairs on signal pathway 154,and the inverted signals of the complementary pairs on signal pathway156, to the LSB current cell matrix 172.

[0030] One complementary output pair of MSB latch circuitry 140corresponds to the single bit in the output of MSB unit encoder 130 thatis always in the off state as described earlier. Similarly, onecomplementary output pair of LSB latch circuitry 142 corresponds to thesingle bit in the output of LSB unit encoder 132 that is always in theoff state. In some embodiments such an output pair corresponding to analways-off input is not communicated to the analog conversion circuitry.Other embodiments may communicate such an output pair to the analogconversion circuitry in modified form; i.e., the outputs are notcomplementary but are both fixed in the off state. One skilled in theart recognizes that these and other embodiments may be employed in thepractice of the invention.

[0031] Analog Conversion Circuitry

[0032] The analog conversion circuitry 160 prominently contains aplurality of current cells. Differential outputs from each of thecurrent cells are summed at current summing nodes 190, 192, and drive apair of load resistors that are centered at ground (not shown). Thecurrent driving the load resistors is related to the full-scale currentin almost identical proportion as the original binary number relates tothe maximum binary number the DAC 100 accommodates, i.e., 1023. Thus,the current represents an analog approximation of the original number inbinary (digital) form.

[0033] The individual current cells obtain current from master currentbias circuit 162. FIG. 2 is a schematic diagram of the master currentbias circuit used in the present embodiment. The master current biascircuit 162 uses a pair of low voltage, wide swing, high impedancecurrent mirrors. The mirrors receive current from some stable currentsource at the external current bias connection point 161. The stablecurrent source may be, for example, a bandgap reference current tap. Themirrors take in the current source and translate it to a current sinkfor use by the individual current cells. The current mirror and thebandgap reference current tap are well known in the art.

[0034] The presently described embodiment organizes the plurality ofcurrent cells into two sets of current cells, each physically configuredas a matrix. MSB current cell matrix 170 is controlled by thecomplementary output signal pairs of MSB latch circuitry 140. LSBcurrent cell matrix 172 is controlled by the complementary output signalpairs of LSB latch circuitry 142.

[0035] The MSB current cell matrix 170 is a coarse conversion matrix. Inthe presently described embodiment the MSB matrix 170 is fabricated onan integrated circuit die in an eight column by eight row matrixconfiguration, providing 64 cells. One sixty-fourth ({fraction(1/64)}=½⁶) of the nominal full-scale DAC output current is distributedequally to each of 63 of the 64 current cells in MSB matrix 170. One ofthe 64 current cells remains unused. The unused one sixty-fourth of thefull-scale current supplies all of the current cells in the LSB currentcell matrix 172. The full-scale current of the present embodiment is onthe order of 20 milliamps.

[0036] Each of the cells is controlled by one of the complementaryoutput signal pairs of MSB latch circuitry 140 to deliver its portion ofthe full-scale current to one or the other of the current summing nodes190, 192 at the output of the DAC 100. An exception in the presentembodiment is the unused current cell. Its control input signals are notcomplementary, but rather are both fixed in the off state. This preventsthe cell from making a contribution to either summing node.

[0037] The LSB current cell matrix 172 is a fine conversion matrix. Inthe presently described embodiment the LSB matrix 172 is fabricated onan integrated circuit die in an eight row by two column matrixconfiguration, providing 16 cells. One sixteenth ({fraction (1/16)}=½⁴)of the one sixty-fourth of the nominal full-scale current unused by theMSB current cell matrix 170 is distributed equally to each of 15 of the16 current cells in LSB matrix 172. One of the 16 current cells remainsunused to accommodate a zero value. (The unused {fraction (1/1024)}(½⁴⁺⁶) of the nominal full-scale current remains unused resulting in anoperational full-scale current just slightly below the nominal value.)

[0038] In similar fashion to the MSB cell matrix 170, each of the cellsin the LSB current cell matrix 172 is controlled by one of thecomplementary output signal pairs of LSB latch circuitry 142 to deliverits portion of the full-scale current to one or the other of the currentsumming nodes 190, 192 at the output of the DAC 100. As above, anexception is the unused current cell. Its control input signals are notcomplementary, but rather are both fixed in the off state. This preventsthe cell from making a contribution to either summing node.

[0039] Employing such equal current-based weighting to each current cellin a matrix provides faster settling time than with, for example,voltage divider DAC designs. This improves AC and DC performance andrepresents an advantage of the present invention.

[0040] Current Cell Detail

[0041]FIG. 3 is a schematic diagram of a current cell circuit. The MSBmatrix (170 of FIG. 1) and the LSB matrix (172 of FIG. 1) both employthe current cell architecture represented in the schematic for theirindividual current cells. Because a current cell in the MSB matrix 170conducts some multiple of the current conducted by an LSB matrix 172current cell, however, transistor sizes are scaled accordingly.

[0042] Each current cell 300 as depicted in FIG. 3 is a fullydifferential current switch, which takes in a pair of signals havingcomplementary binary states, and passes a differential signal out to twoloads having a common DC reference.

[0043] Each current cell 300 comprises a differential current switchcircuit 310, a regulated cascode current source 320, a master currentbias slave circuit 325, a DC reference voltage connection 370, inputsfor a complementary signal pair 350, 352, differential outputs 354, 356,electrical ground connection 378, and master current bias connections372, 374, 376. The differential current switch 310 further comprisescurrent source connection 312, switching transistors 330, 332, andcharge canceling transistors 334, 336. The regulated cascode currentsource 320 further comprises cascode transistors 340, 342, DC bias node341, impedance multiplier transistor 344, and capacitance element 346.The master current bias slave circuit 325 further comprises mastercurrent supply bias mirror transistors 360, 362.

[0044] Differential current switch 310 receives current from theregulated cascode current source 320 at current source connection 312.The source of each of PMOS switching transistors 330, 332 is connectedto current source connection 312. The drain of switching transistor 330is connected to the source of charge canceling transistor 334. Thesource and drain of charge canceling transistor 334 are short-circuited,and the drain is further connected to one of the differential outputs356. Switching transistor 330 has its gate connected to an input 350 forone of the signals of a complementary pair. Charge canceling transistor334, in contrast, has its gate connected to an input 352 for thecomplementary signal of the pair.

[0045] In similar, but complementary, fashion, the drain of switchingtransistor 332 is connected to the source of charge canceling transistor336. The source and drain of charge canceling transistor 336 areshort-circuited, and the drain is further connected to the remainingdifferential output 354. Switching transistor 332 has its gate connectedto input 352 for one of the signals of the complementary pair. Chargecanceling transistor 336 has its gate connected to an input 350 for thecomplementary signal of the pair.

[0046] Accordingly, it can be seen that the gates of the switchingtransistors 330, 332 are driven by complementary signals, as are thegates of the charge canceling transistors 334, 336.

[0047] Each of charge canceling transistors 334, 336 is roughly equal toone half the size of its corresponding switching transistor, i.e., 330,332, respectively. The charge canceling transistors 334, 336 cancelunwanted channel charge injection and minimize unwanted clockfeed-through from the gate stimulus, by canceling charges between theswitch transistor and the complementarily switched charge cancelingtransistor. This configuration achieves minimal unwanted feed-through tothe loads coupled to the differential outputs 354, 356. The reducedfeed-through minimizes harmonic distortion, improving spurious freedynamic range (SFDR). This represents a further advantage of the presentinvention.

[0048] Regulated cascode current source 320 delivers current to thedifferential current switch 310 at current source connection 312.Regulated cascode current source 320 uses a very high impedance cascodeconfiguration (e.g., 100 Megaohms) to source up to the full value of thecurrent through either leg of the differential current switch 310depending on the value of the complementary input code. The cascodeconfiguration employs two series cascoded transistors 340, 342. Thesource of cascode transistor 340 is connected to a common DC referencevoltage connection 370. The drain of cascode transistor 340 is connectedto the source of cascode transistor 342 at DC bias node 341. The drainof cascode transistor 342 is connected to current source connection 312.

[0049] By utilizing a regulated cascode current source configuration thestacked transistor area can be kept smaller than with a conventionalstacked cascode configuration, while still maintaining high outputimpedance. The smaller area also serves to impair either activeswitching signal from feeding through the drain-source path of thecascode transistor 342 and ultimately to DC bias node 341. This improvesdifferential non-linearity (DNL) characteristics by reducing disturbanceat DC bias node 341. This represents a further advantage of the presentinvention.

[0050] The DC bias node 341 at which both cascode transistors 340, 342meet is connected to the gate of impedance multiplier transistor 344.The drain of transistor 344 is fed back to the gate of cascodetransistor 342. The source of transistor 344 is connected to a common DCreference voltage connection 370.

[0051] Impedance multiplier transistor 344 operates to effectivelymultiply the high impedance of the cascode output by a factor of thegain of the transistor 344. Transistor 344 further adds an additionalpath for unwanted charge at connection 312 to travel, and so reducesunwanted signal injection to the common DC bias node 341. Capacitanceelement 346 is connected in parallel with impedance multipliertransistor 344, increasing transient stability while further minimizingunwanted signal feed-through to the DC bias node 341. So increasing thestability of common DC bias node 341 reduces glitch energy transferredto the loads coupled to the differential outputs 354, 356, againreducing harmonic distortion, and improving SFDR. These operationalcharacteristics represent yet another advantage of the presentinvention.

[0052] Further, the higher impedance of the individual cells than seenin earlier DAC designs helps maintain a higher overall impedance as seenby the load when the differential outputs of all the current cells areconnected in parallel to the current summing nodes. The higher impedancecontributes to lower integral non-linearity (INL) characteristics, afurther advantage of the present invention.

[0053]FIG. 4 illustrates the layout orientation of current cell matricesand the relative switching order among the cells in each matrix. Asdescribed earlier, the MSB current cell circuitry 170 is configured as amatrix of 8 rows by 8 columns. The number appearing within each cell ofthe MSB matrix 170 in FIG. 3 indicates the switching order of the cell.In accordance with the unit encoding described earlier in relation tothe encoder circuitry (110 of FIG. 1), for any cell switched on withinthe MSB matrix 170, all other cells within the MSB matrix 170 having aswitching order number lower than that of the switched on cell, willalso be switched on. The complementary signal pairs communicated fromencoder circuitry (110 of FIG. 1) via signal paths (150, 152 of FIG. 1)are connected to the individual current cells of MSB matrix 170 toproduce the switching order depicted in FIG. 4. Cell 410 is the unusedcell of the matrix 170 as described above in reference to FIG. 1.

[0054] The LSB current cell circuitry 172 is configured as a matrix of 8rows by 2 columns. The number appearing within each cell of the LSBmatrix 172 in FIG. 3, similarly, indicates the switching order of thecell. As with the MSB matrix 170, for any cell switched on within theLSB matrix 172, all other cells within the LSB matrix 172 having aswitching order number lower than that of the switched on cell, willalso be switched on. The complementary signal pairs communicated fromencoder circuitry (110 of FIG. 1) via signal paths (154, 156 of FIG. 1)are connected to the individual current cells of LSB matrix 172 toproduce the switching order depicted in FIG. 4. Cell 412 is the unusedcell of the matrix 172 as described above in reference to FIG. 1.

[0055] The cell switching order assignments depicted in FIG. 4 utilizehierarchical gradient symmetry cancellation techniques. Such a layoutorientation has the advantage of reducing INL attributable toprocess-related surface gradients. This represents a further advantageof the present invention.

[0056] Various modifications to the preferred embodiment can be madewithout departing from the spirit and scope of the invention. Forexample, the design could be extended or contracted to accommodate abinary input number having more or fewer than 10 bits. Thus, theforegoing description is not intended to limit the invention which isdescribed in the appended claims in which:

What is claimed is:
 1. A current cell circuit for use indigital-to-analog conversion, comprising: a regulated cascode currentsource; and a differential current switch coupled to the regulatedcascode current source, having first and second inputs for receivingcomplementary input signals, first and second outputs for presentingdifferential output signals, and a current source connection.
 2. Thecurrent cell of claim 1 wherein the regulated cascode current sourcefurther comprises: a first cascode transistor having its source coupledto a DC reference source; and a second cascode transistor having itssource coupled to the drain of the first cascode transistor, and itsdrain coupled to the current source connection of the differentialcurrent switch.
 3. The current cell of claim 2 wherein the regulatedcascode current source further comprises an impedance multiplier.
 4. Thecurrent cell of claim 3 wherein the impedence multiplier comprises afeedback transistor having its gate coupled to the drain of the firstcascode transistor and the source of the second cascode transistor, andits drain coupled to the gate of the second cascode transistor.
 5. Thecurrent cell of claim 4 wherein the source of the feedback transistor iscoupled to the DC reference source.
 6. The current cell of claim 5wherein the regulated current source further comprises a capacitanceelement having a first connection coupled to the DC reference source,and a second connection coupled to the gate of the second cascodetransistor.
 7. The current cell of claim 1 wherein the differentialcurrent switch further comprises: a first switch element disposedbetween the current source connection and the first output; and a secondswitch element disposed between the current source connection and thesecond output.
 8. The current cell of claim 7 wherein the differentialcurrent switch further comprises first and second charge cancelingelements, each for coupling one of the switch elements to its respectiveoutput.
 9. The current cell of claim 8 wherein the first switch elementcomprises a transistor having its gate coupled to the first input andits source coupled to the current source connection, and wherein thesecond switch element comprises a transistor having its gate coupled tothe second input and its source coupled to the current sourceconnection.
 10. The current cell of claim 9 wherein the first chargecanceling element comprises a transistor having its source and drainshort-circuited, its source coupled to the drain of the first switchelement transistor, and its gate coupled to the second input, andwherein the second charge canceling element comprises a transistorhaving its source and drain short-circuited, its source coupled to thedrain of the second switch element transistor, and its gate coupled tothe first input.
 11. The current cell of claim 5 wherein thedifferential current switch further comprises: a first switch elementdisposed between the current source connection and the first output; anda second switch element disposed between the current source connectionand the second output.
 12. The current cell of claim 11 wherein thedifferential current switch further comprises first and second chargecanceling elements, each for coupling one of the switch elements to itsrespective output.
 13. The current cell of claim 12 wherein the firstswitch element comprises a transistor having its gate coupled to thefirst input and its source coupled to the current source connection, andwherein the second switch element comprises a transistor having its gatecoupled to the second input and its source coupled to the current sourceconnection.
 14. The current cell of claim 13 wherein the first chargecanceling element comprises a transistor having its source and drainshort-circuited, its source coupled to the drain of the first switchelement transistor, and its gate coupled to the second input, andwherein the second charge canceling element comprises a transistorhaving its source and drain short-circuited, its source coupled to thedrain of the second switch element transistor, and its gate coupled tothe first input.
 15. A digital-to-analog converter circuit comprising:encoder circuitry for producing a plurality of complementary pairs ofsingle-bit outputs; a master current supply; a first current summingnode; a second current summing node; a plurality of current cells, eachcurrent cell having: a correspondence with one of the plurality ofcomplementary pairs of single-bit outputs; a regulated cascode currentsource coupled to the master current supply; and a differential currentswitch having a current source connection coupled to the regulatedcascode current source, a first input coupled to the first single-bitoutput of the corresponding complementary pair, a second input coupledto the second single-bit output of the corresponding complementary pair,a first output coupled to the first current summing node, and a secondoutput coupled to the second current summing node.
 16. Thedigital-to-analog converter of claim 15 wherein: the encoder circuitryis further for receiving a multi-bit, binary number; the plurality ofcomplementary pairs of single-bit outputs belong to two or more sets,each set corresponding to a segment of a received binary number; and theplurality of current cells belong to two or more sets, each setcorresponding to one of the sets of complementary single-bit outputs.